Senior Design Verification Specialist

3 days ago

Anantapur, Andhra Pradesh, India beBeeVerification Full time ₹ 70,00,000 - ₹ 1,36,60,000
Design Verification Expert

We are seeking a highly experienced and skilled Design Verification Engineer to join our team.

  • Lead and contribute to the verification of complex IP blocks or SoC subsystems, ensuring high-quality designs that meet specifications.
  • Develop test plans, verification strategies, and coverage metrics based on design specifications, driving closure and improvement.
  • Build and maintain constrained-random and directed testbenches using SystemVerilog/UVM, leveraging expertise in RTL simulation tools.
  • Collaborate with architects, designers, and other verification engineers to identify and debug design issues, providing technical guidance and mentorship to junior team members.
  • Develop and maintain verification infrastructure, scripts, and regression systems, ensuring efficient and effective workflows.
  • Perform functional and code coverage analysis, driving closure and improving overall quality.

Required Skills and Qualifications:

  • B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or Computer Engineering, with a strong foundation in digital logic and circuit design.
  • 8–14 years of hands-on experience in ASIC/SoC verification, with a proven track record of delivering high-quality results.
  • Strong expertise in SystemVerilog, UVM, and RTL simulation tools, with a solid understanding of verification methodologies and functional coverage.
  • Familiarity with scripting languages (Python, Perl, or TCL) for automation, as well as version control and CI/CD systems.

Preferred Qualifications:

  • Experience in formal verification or emulation, with a focus on improving design quality and efficiency.
  • Familiarity with industry-standard protocols like PCIe, USB, DDR, AMBA (AXI/AHB/APB), and exposure to post-silicon bring-up and validation.
About This Role

This position is responsible for leading and contributing to the verification of complex IP blocks or SoC subsystems.

The ideal candidate will have a strong background in digital logic and circuit design, as well as experience with SystemVerilog, UVM, and RTL simulation tools.

Key Responsibilities

The key responsibilities of this role include:

  • Developing test plans, verification strategies, and coverage metrics based on design specifications.
  • Building and maintaining constrained-random and directed testbenches using SystemVerilog/UVM.
  • Collaborating with architects, designers, and other verification engineers to identify and debug design issues.
  • Developing and maintaining verification infrastructure, scripts, and regression systems.
  • Performing functional and code coverage analysis.

This role requires a strong understanding of verification methodologies and functional coverage, as well as experience with scripting languages (Python, Perl, or TCL) for automation.

Qualifications

To be considered for this role, you should have:

  • B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or Computer Engineering.
  • 8–14 years of hands-on experience in ASIC/SoC verification.
  • Strong expertise in SystemVerilog, UVM, and RTL simulation tools.
  • Familiarity with scripting languages (Python, Perl, or TCL) for automation.

PREFERRED QUALIFICATIONS:

  • Experience in formal verification or emulation.
  • Familiarity with industry-standard protocols like PCIe, USB, DDR, AMBA (AXI/AHB/APB).

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