Senior Digital Test Architect

2 days ago

Tiruppur, Tamil Nadu, India beBeeDesign Full time ₹ 2,00,00,000 - ₹ 2,50,00,000
Job Title: Lead DFT Engineer

A high-performing Lead DFT Engineer is required to oversee the development and implementation of complex digital test architectures for SoC/ASIC designs.

The ideal candidate will have a proven track record in driving innovation, mentoring junior engineers, and collaborating with cross-functional teams to deliver world-class testability and manufacturability.

Key Responsibilities:
  • Develop and drive DFT strategies and architectures for multiple ASIC/SoC projects.
  • Lead the implementation and verification of DFT features like scan insertion and compression, ATPG pattern generation, MBIST, boundary scan, and IJTAG.
  • Manage end-to-end DFT flows from RTL to gate-level netlist and silicon bring-up.
  • Collaborate with RTL, STA, PD, and test engineering teams for seamless integration.
  • Perform pattern generation, fault simulation, and debug test coverage gaps.
  • Own DFT signoff, timing closure (DFT-related paths), and ATE pattern delivery.
  • Support silicon bring-up, test vector validation on ATE, and yield optimization.
  • Mentor and guide junior DFT engineers; conduct design reviews and training sessions.
Required Skills and Qualifications:
  • Bachelor's or Master's degree in Electronics, Electrical, or VLSI Design.
  • 7+ years of experience in DFT for complex ASIC or SoC designs.
  • Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.
  • Hands-on experience with DFT tools such as Synopsys, Siemens EDA, and Cadence.
  • Strong knowledge of RTL design, STA, and synthesis flows.
  • Proficient in scripting languages (Python, Perl, Tcl) for flow automation.
  • Deep understanding of silicon test challenges and test coverage improvement.
Benefits:
  • Competitive salary and leadership exposure.
  • Fast-track growth opportunities and collaboration with top-tier engineers.

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