Chief Verification Architect
3 weeks ago
Leadsoc is a technology company that delivers cutting-edge solutions through innovation and collaboration. As a Senior Design Verification Engineer, you will play a crucial role in leading and executing complex design verification tasks at the IP and subsystem level.
Job Description
- Develop and execute comprehensive verification plans and testbenches using SystemVerilog (SV) and Universal Verification Methodology (UVM).
- Create and maintain high-quality testcases to thoroughly validate design functionality and performance.
- Conduct in-depth debugging of test failures, identify root causes, and propose effective solutions.
- Provide technical guidance and mentorship to team members, fostering a collaborative and innovative work environment.
Requirements
- Strong proficiency in SystemVerilog (SV) and Universal Verification Methodology (UVM).
- Hands-on experience in developing complex verification environments, including testbench components, testcases, and assertions.
- In-depth understanding of digital design concepts and verification methodologies.
- Proven ability to independently debug and analyze complex issues.
- Strong knowledge of industry standard protocols like PCIe and AXI.
Compensation: $120,000 - $180,000 per year
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