Digital Design Engineering Manager for Chip Fabrication
2 weeks ago
Mulya Technologies is a pioneering firm founded by esteemed Silicon Valley veterans, boasting design centers in Santa Clara and Hyderabad. As a Senior Physical Design Manager, you will be part of an elite team responsible for complex chip design, working on server chips and other intricate projects.
The ideal candidate should have hands-on experience with full-chip design, particularly with complex chips targeted at 3nm/5nm processes. Your expertise should span synthesis, floor planning, power grid design, place and route, clock tree synthesis, timing closure, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure, and physical design project management.
- Work on hierarchical chip implementation (Blocks and Top) including floor planning, partitioning, power planning, bump planning, and integration of sub-blocks and custom macros/IPs.
- Physical implementation of blocks and top-level timing IR analysis and closure.
- Develop and maintain physical design flows and methodologies.
To succeed in this role, you should possess:
- B.Tech/M.Tech from a reputable university with 10-15+ years of relevant experience.
- Good knowledge of VLSI process and device characteristics.
- Experience in physical design targeted to the 3nm/5nm FinFet process.
- Strong understanding of static timing analysis (STA), EM/IR, and sign-off.
- Hands-on experience with EDA tools such as Innovus, Tempus/PrimeTime-SI, Voltus/RedHawk, StarXT/Quantus, Calibre, LEC etc.
- Excellent software and scripting skills (Python, tcl).
We offer a competitive salary range of $250,000 - $350,000 per year, depending on experience, along with opportunities for professional growth and development in a dynamic and innovative work environment.
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