Senior Digital Fault Tolerant Engineer

2 days ago


Vijayawada, Andhra Pradesh, India beBeeDigitalFaultTolerant Full time ₹ 10,00,000 - ₹ 15,00,000
Job Title

We are seeking a highly skilled engineer to join our team as a Senior Digital Fault Tolerant Engineer.

  • The ideal candidate will have experience in developing and implementing DFT architecture for ASIC/SoC designs.

Key Responsibilities:

  1. Design and implement scan chains, boundary scan (JTAG), MBIST, LBIST, and other test structures.
  2. Collaborate with RTL and physical design teams to ensure seamless integration of DFT features.
  3. Generate and validate test patterns using ATPG tools for stuck-at, transition, and path delay faults.
  4. Perform fault simulation and coverage analysis to optimize test quality.
  5. Support silicon bring-up and debug of test-related issues.
  6. Work with ATE teams to develop test programs and support production testing.

Requirements:

  • 3+ years of experience in digital fault tolerant engineering.
  • Strong knowledge of DFT techniques and tools.
  • Experience working with RTL and physical design teams.
  • Excellent communication and collaboration skills.

What We Offer:

  • A dynamic and collaborative work environment.
  • Opportunities for professional growth and development.
  • A competitive salary and benefits package.

How to Apply:

If you are a motivated and talented engineer looking for a new challenge, please submit your resume and cover letter for consideration.



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