Senior Engineer for Advanced Chip Testing

2 days ago

Hyderabad, Telangana, India beBeeSoftware Full time ₹ 1,36,56,250 - ₹ 2,51,26,000
Job Role

We are seeking a skilled professional to drive the implementation of Design for Test (DFT) architecture in Wireless System-on-Chip (SoC) chips. As an Associate Staff Engineer, you will play a key role in developing and implementing ATPG architecture, design, implementation, verification, and deployment to silicon testing.

Main Responsibilities
  • Develop and implement ATPG architecture, design, implementation, verification, and deployment to silicon testing.
  • Design, implement, and verify MBIST for all memories in the SoC.
  • Generate and debug DFT patterns on testers.
Required Skills and Qualifications
  • 8-10 years of experience in full-chip DFT working with multiple design tape outs.
  • Expert knowledge of DFT architecture on complex designs with multiple clock domains.
  • Experience in ATPG for pattern generation and simulation of test transition faults, stuck-at, IDDQ, at-speed faults.
  • Hands-on experience in industry-standard DFT tools - Mentor Tessent suite or Synopsys DFT compiler.
  • Block-level and chip-level SCAN insertion, DRC, coverage analysis, and improvements.
  • Expertise in scan compression (EDT/OPMISR+), MBIST, ATPG implementation, and verification.
  • Good knowledge of cross-functional domains (SYN, LEC, STA, PD) with ownership of constraint developments & LEC.
  • Ability to develop and automate flows and scripts in Perl/Tcl to enhance DFT methodologies & process.
  • Experience working with cross-functional global teams.
  • Experience in low-power DFT requirements.
  • Experience in low-power MBIST architectures and memory testing.
Benefits
  • Opportunity to work on cutting-edge technology.
  • Collaborative team environment.
  • Professional growth and development opportunities.

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