
Chief Engineering Officer for Advanced Semiconductor Solutions
5 days ago
Key Responsibilities Include:
- Develop and Implement Advanced Physical Layouts for Semiconductor Devices at Nanometer Nodes.
- Collaborate with Customers to Resolve Critical Design Issues and Achieve Performance, Area, and Power Targets.
- Drive Methodologies and Flows for Placement, Clock-Tree Synthesis, and Routing.
- Provide Expert Technical Support and Training to Customers on Physical Design Tools and Best Practices.
Required Expertise:
- Deep Understanding of Place and Route Flow, Including Placement Guidelines, Timing Optimizations, and Static Timing Analysis.
- Experience with Hierarchical Designs, Low-Power Implementation, and Interface Development with RTL Designers.
- Knowledge of Floor Plan Design, Hard Macro Placement, Pad Ringing, Power Grid Design, and Custom Analog Routes.
- Expertise in Constraint Development, Parasitic Extraction, Sign-Off Requirements, and Physical Verification Techniques.
- Proficiency in DRC, LVS, and Chip Finishing Procedures.
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