Subsystem Timing Engineer

3 days ago

Coimbatore, Tamil Nadu, India beBeeSubsystemTiming Full time ₹ 2,50,00,000 - ₹ 3,00,00,000
Subsystem Timing Engineer

 

We are seeking a highly skilled Subsystem Timing Engineer to lead Static Timing Analysis (STA) and Place and Route (PNR) activities for complex subsystems. This role requires expertise in timing closure, floorplanning, placement, clock tree synthesis, routing, and physical verification for high-complexity subsystems.

 

The ideal candidate will have 10+ years of experience in STA and PNR for complex subsystems within ASIC/SoC design, including advanced technology nodes (7nm or below). They should be proficient in scripting languages (Tcl, Perl, Python) for automating STA and PNR flows across multiple subsystem blocks.

 

This position involves collaboration with cross-functional teams to resolve design, timing, and physical implementation challenges specific to complex subsystem integration. The successful candidate will also have excellent communication skills to present technical solutions and lead discussions with internal teams and customers.

 

Key Responsibilities:

  • Lead STA and PNR activities for complex subsystems, ensuring robust timing closure and physical implementation with a focus on power, performance, and area optimization.
  • Develop and refine methodologies for STA and PNR tailored to the unique challenges of large, multi-interface, or mixed-signal subsystems.
  • Drive automation and validation of timing and physical design data across subsystem boundaries.
  • Mentor and guide junior engineers, fostering technical growth and knowledge sharing within subsystem teams.
  • Collaborate cross-functionally to resolve design, timing, and physical implementation challenges specific to complex subsystem integration.

 

Required Skills and Qualifications:

  • 10+ years of experience in STA and PNR for complex subsystems within ASIC/SoC design, including advanced technology nodes (7nm or below).
  • Demonstrated expertise in STA tools (e.g., Synopsys PrimeTime, Cadence Tempus) and PNR tools (e.g., Synopsys ICC2, Cadence Innovus) applied to large, multi-block or hierarchical subsystems.
  • Proven track record in timing closure, floorplanning, placement, clock tree synthesis, routing, and physical verification for high-complexity subsystems.
  • Proficient in scripting languages (Tcl, Perl, Python) for automating STA and PNR flows across multiple subsystem blocks.
  • Deep understanding of SoC design flows, with experience collaborating across frontend, physical design, and verification teams to integrate complex subsystems.

 

Benefits:

  • A dynamic work environment that encourages innovation and collaboration.
  • The opportunity to work with cutting-edge technologies and complex systems.
  • A competitive compensation package and benefits program.

 

Others:

The selected candidate will undergo a thorough evaluation process, which includes a comprehensive review of their qualifications, skills, and experience.

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