Digital Systems Architect

1 week ago

Greater Noida, Uttar Pradesh, India beBeeSoftware Full time € 1,40,000 - € 1,87,000

Transforming the world with technology is at the heart of our mission.

About This Role
  • This position offers a unique opportunity to lead and contribute to the design and delivery of core subsystems across multiple SOC generations as part of a highly collaborative platform design team.
  • With deep experience in RTL design and SoC-level integration, this role plays a critical part in enabling high-performance, low-power, and functionally safe systems across diverse markets.

Responsibilities:

Main Responsibilities
  • Collaborate closely with systems architects and microarchitects to define high-level, implementable SOC specifications that meet project goals.
  • Take ownership of end-to-end IP Sub-system RTL delivery while analyzing and optimizing design for power, performance, and area targets.
  • Lead the RTL design and integration of Sub-system supporting complex architectures with multi-core, multi-reset domains.
  • Demonstrate strong proficiency with frontend flows including LINT, CDC, Synthesis, DFT, and Static Timing Analysis STA.
  • Drive the development of robust Safety Security and Debug architectures for advanced SOCs with multiple interconnects.
  • Design and integrate standard interface protocols like AHB AXI and memory interfaces like RAM Flash.
  • Foster cross-functional collaboration with DFT Physical Design Verification Emulation and Validation teams to ensure first-time right silicon and on-time project delivery.
  • Support silicon bring-up debug and post-silicon performance analysis through detailed simulation and system-level integration.
  • Continuously evaluate and adopt new design methodologies and best practices to improve productivity and shift-left the design cycle.
  • Utilize scripting to manage design flows and automate repetitive tasks for improved efficiency.
  • Mentor junior engineers and provide technical leadership and guidance across multiple design projects.
  • Contribute to the innovation quotient of the team via Patents Industry-standard publications etc.

Requirements:

Essential Qualifications
  • Bachelor's or Master's degree or equivalent experience in Electronics Electrical Engineering with 12 years of RTL design experience.
  • Proven expertise in Verilog System Verilog RTL design integration and microarchitecture.
  • Strong understanding of SOC architecture AMBA protocols AXI AHB APB clock reset domains and memory sub-systems.
  • Experience with EDA tools for synthesis LINT CDC RDC and timing analysis.
  • Familiarity with formal verification techniques static dynamic power checks.
  • Proficiency in scripting and automation using Python.
  • Excellent leadership communication skills.
  • Experience working with global cross-functional teams.
  • Working knowledge of safety-critical design flows in automotive systems.
  • Knowledge of Automotive Functional Safety ISO26262 is a plus.

We strive to innovate for a future that is smarter greener and more responsible. Join us and start shaping the future.

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