
Senior Digital Fault Tolerance Specialist
4 days ago
Digital Fault Tolerance Expert
The ideal candidate for this role will have a strong background in Digital Fault Tolerance (DFT) concepts, with experience in developing and implementing DFT strategies for complex designs. He/she will be responsible for leading cross-functional teams in designing and verifying testbenches, collaborating with engineers to define and implement scan insertion, ATPG, coverage analysis, and transition delay test coverage analysis.
Key Responsibilities
- Develop and implement comprehensive DFT strategies for complex digital designs.
- Lead the design and verification of testbenches for digital systems.
- Collaborate with engineering teams to define and implement advanced DFT techniques, including scan insertion, ATPG, coverage analysis, and transition delay test coverage analysis.
- Design and implement memory test validation using MBIST insertion.
- Expertise in scripting languages such as Perl and Shell is required.
- Proficiency in RTL and Gate level simulations of scan and MBIST test vectors is necessary.
- Equivalence check and DFT Design Rule Check (DRC) rules implementation in RTL lint tools and ATPG tools are also required.
Requirements
- Strong understanding of DFT concepts and their application in digital design.
- Hands-on experience in scan insertion, ATPG, coverage analysis, and transition delay test coverage analysis.
- Advanced expertise in scripting languages such as Perl and Shell.
- Proficiency in RTL and Gate level simulations of scan and MBIST test vectors.
- Knowledge of equivalence check and DFT DRC rules in RTL lint tools and ATPG tools.
- Excellent communication and teamwork skills.
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