
Senior SoC Design Optimization Specialist
1 week ago
Job Title: STA Engineer
Key Responsibilities:
- Timing Closure Expertise: We are seeking a skilled and motivated STA Engineer to drive the RTL-to-GDSII implementation of complex SoC blocks or full-chip designs, focusing on performance, power, and area (PPA) optimization and signoff closure.
- DFT Modes in Timing Closure: The successful candidate will be responsible for ensuring accurate and efficient design closure by creating and maintaining constraints.
- Design Optimization: Utilizing DFT modes to optimize design performance and reduce costs.
We are looking for a highly motivated and experienced STA Engineer who can deliver high-quality results while working efficiently in a collaborative environment.
Please share your CV with us if you are interested in this challenging role.
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