
Career Opportunity in Advanced Subsystem Design
1 day ago
We are seeking a highly skilled Senior Static Timing Analyst to lead complex subsystems in Static Timing Analysis (STA) and Place and Route (PNR) activities.
The ideal candidate will have 10+ years of experience in STA and PNR for complex subsystems within ASIC/SoC design, including advanced technology nodes.
Key Responsibilities:
- Lead STA and PNR activities for complex subsystems ensuring robust timing closure and physical implementation with a focus on power, performance, and area optimization.
- Develop and refine methodologies for STA and PNR tailored to the unique challenges of large, multi-interface, or mixed-signal subsystems.
- Drive automation and validation of timing and physical design data across subsystem boundaries.
- Mentor and guide junior engineers fostering technical growth and knowledge sharing within subsystem teams.
- Collaborate cross-functionally to resolve design, timing, and physical implementation challenges specific to complex subsystem integration.
- 10+ years of experience in STA and PNR for complex subsystems within ASIC/SoC design, including advanced technology nodes.
- Expertise in STA tools and PNR tools applied to large, multi-block or hierarchical subsystems.
- Proven track record in timing closure, floorplanning, placement, clock tree synthesis, routing, and physical verification for high-complexity subsystems.
- Proficient in scripting languages for automating STA and PNR flows across multiple subsystem blocks.
- Deep understanding of SoC design flows, with experience collaborating across frontend, physical design, and verification teams to integrate complex subsystems.
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