
Senior Digital Fault Tolerant Engineer
2 days ago
We are seeking a highly skilled and experienced DFT Engineer to join our team.
- Main Responsibilities:
- Develop and implement DFT architecture with a focus on MBIST for advanced SoCs.
- Integrate MBIST IPs, generate test insertion and verification infrastructure.
- Work on DFT planning, insertion, simulation, and pattern generation.
- Perform ATPG and MBIST pattern generation and debug failures from silicon bring-up.
- Collaborate with RTL, Physical Design, and Verification teams throughout the design cycle.
- Support silicon bring-up and yield improvement activities post-silicon.
- Ensure high coverage and test quality in scan and MBIST.
Requirements
- Essential Qualifications:
- B.E/B.Tech or M.E/M.Tech in Electronics or related field.
- Minimum 7+ years of hands-on experience in DFT with a strong focus on ATPG, SCAN and MBIST
- Proficient in tools such as Synopsys DFT Compiler, Tessent (Mentor), or equivalent.
- Solid understanding of scan insertion, ATPG, boundary scan, and JTAG.
- Experience with memory test algorithms, repair analysis, and pattern generation.
- Familiarity with scripting languages (TCL, Perl, Python) for automation.
- Personal Attributes:
- Strong analytical and problem-solving skills with the ability to work independently
About Us
We offer a dynamic and supportive work environment that fosters innovation and growth. Our team is passionate about delivering high-quality solutions that meet the needs of our clients. If you are a motivated and talented individual who is looking for a new challenge, we encourage you to apply.
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