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Senior ASIC/FPGA Design Engineer

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Job Description

Design and implement Digital Fault Tolerance (DFT) architectures for complex semiconductor devices.

  • Develop innovative scan chain designs and boundary scan (JTAG) mechanisms to facilitate efficient testing.
  • Collaborate with cross-functional teams, including RTL and physical design experts, to ensure seamless integration of DFT features.
  • Utilize ATPG tools to generate and validate test patterns for various fault types.