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17 hours ago
We are seeking an experienced timing optimization specialist to lead our team in the development of complex subsystems. The ideal candidate will have a strong background in STA and PNR, with a focus on power, performance, and area optimization.
Key Responsibilities:
- Lead STA and PNR activities for complex subsystems, ensuring robust timing closure and physical implementation.
- Develop and refine methodologies for STA and PNR tailored to large, multi-interface, or mixed-signal subsystems.
- Drive automation and validation of timing and physical design data across subsystem boundaries.
- Mentor and guide junior engineers, fostering technical growth and knowledge sharing within subsystem teams.
- Collaborate cross-functionally to resolve design, timing, and physical implementation challenges specific to complex subsystem integration.
- Exhibit excellent communication skills to present technical solutions and lead discussions with internal teams and customers.
Required Skills and Qualifications:
- 10+ years of experience in STA and PNR for complex subsystems within ASIC/SoC design, including advanced technology nodes.
- Demonstrated expertise in STA tools (e.g., Synopsys PrimeTime, Cadence Tempus) and PNR tools (e.g., Synopsys ICC2, Cadence Innovus) applied to large, multi-block or hierarchical subsystems.
- Proven track record in timing closure, floorplanning, placement, clock tree synthesis, routing, and physical verification for high-complexity subsystems.
- Proficient in scripting languages (Tcl, Perl, Python) for automating STA and PNR flows across multiple subsystem blocks.
- Deep understanding of SoC design flows, with experience collaborating across frontend, physical design, and verification teams to integrate complex subsystems.
Benefits:
- Pursue challenging projects that drive innovation and growth.
- Cultivate expertise in cutting-edge technologies and methodologies.
- Expand professional network through collaboration with industry leaders.
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