Lead RTL-Centric DFT Methodology Engineer

3 days ago


Bengaluru, Karnataka, India Mulya Technologies Full time
Mulya Technologies is accelerating the critical data communication at the heart of our digital world. Our technology powers product progress in data-demanding industries, including data centers, networking, storage, AI, 5G wireless infrastructure, and autonomous vehicles. We are seeking a senior member to develop flows across all company departments and projects. The ideal candidate will have a good understanding of Verilog/VHDL and System Verilog, exposure to CAD and automation, and experience with main DFT standards such as JTAG and BIST techniques.

The role involves architecting methodologies and flows for an integrated environment, developing automated verification test benches and sequence creation for DFT IP, and building IP/block and SoC level scan insertion flows and script ATPG retargeting procedures. Additionally, the candidate will create automated QoR checks for implementation quality control, write static timing constraints, and devise flows for bulletproof timing checks. Furthermore, they will hire, train, and lead DFT engineers in daily tasks and activities to fulfill company road map requirements.

A successful candidate will have a track record in integrating custom made DFT logic for complex SoCs and CoWoS designs, experience in SoC and IP/Block level scan insertion and ATPG, and experience in scripting/reviewing SCAN/MBIST timing constraints. A good understanding of DFT EDA tools from Tessent, SNPS, and Cadence is valuable. This role offers a competitive salary of $150,000 - $200,000 per year, depending on qualifications and experience, along with a great compensation package, restricted stock units, provisions to pursue advanced education, medical insurance, and a hybrid work environment.

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