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DFT Engineer Lead for Arm Silicon Verification
1 month ago
About the Role
- Architect and implement innovative DFT methods for test chips and hard macros, collaborating with cross-functional teams throughout the project lifecycle.
- Work closely with front-end design and verification teams on DFT RTL level insertion, back-end synthesis, place-and-route, and static-timing-analysis teams on gate level insertion and timing closure, and Test and Debug teams on silicon characterization and validation.
Key Responsibilities
- Possess ≥8+ years of experience in Design for Test, with expertise in Verilog RTL, TCL, and/or Perl.
- Familiarity with Unix/Linux environments and core DFT skills, including Scan compression and insertion, Memory BIST and repair scheme implementation, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate level verification, silicon debug, memory and scan diagnostics.
- Bachelor's or Master's degree or equivalent experience in Electronic Engineering, Computer Engineering, or a related field.
What We Offer
- A competitive salary of $120,000 - $150,000 per annum, depending on location and experience.
- An equal opportunities employer committed to diversity and inclusion.
- Flexible hybrid working arrangements and support for accommodations during the recruitment process.
Nice to Have Skills
- Familiarity with IEEE 1149, 1500, 1687, 1838, Synthesis & Static Timing Analysis, SoC style architectures, and low power design practices.
- Validated understanding of Siemens DFT tools, Arm IP like Cortex CPUs, Mali GPUs, AMBA protocols, CoreLink interconnects, and CoreSight debug.
- Experience with 2.5D and 3D test, as well as Siemens, Cadence, and/or Synopsys DFT and simulation tools.
