
Senior RTL Design Expert
2 days ago
Job opportunity in Bangalore seeks experienced RTL design engineers and verification engineers.
- 5+ years of experience in RTL ASIC, CDC, Lint, Synthesis, Spyglass
- Experience in Logic design / RTL design
- Experience in IP design and integration
Key responsibilities:
- RTL ASIC engineer: 7+ years of experience in ASIC/IP Design
- Design verification engineer: 5-20 years of experience
Requirements:
- IP verification Using SV/UVM
- SOC Verification using C/SV
- Third Party VIP Integration
- Interconnect Protocols: AHB, AXI, APB
- SOC Interfaces: GPIO, SPI, I2C, UART (3+)
- High Speed Serial Interfaces: PCIe Gen 3/4 or USB or MIPI (7+)
- Memory Interfaces: DDR or HBM I/O (10+)
- Coverage Closure: Code, Functional and Toggle
- Tools: Synopsys VCS or Cadence Incisive
- Technical Documentation: Testbench Specification, Test Plan Specification
- Foundry Porting Experience: Technology Library Conversion Related Changes Verification
We value candidates who meet these requirements. Please submit your updated CV to us or connect with the contact person for further discussion.
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