High-Speed SERDES IO PHY Layout Designer

3 days ago

Bengaluru, Karnataka, India beBeeDesigner Full time ₹ 29,70,000 - ₹ 43,50,000

We are seeking a highly skilled and technically sound High-speed SERDES IO PHY Layout designer with 12-15 years of experience.

This individual will develop and optimize Serdes PHY, analog and mixed-signal IC layouts, ensuring high performance and manufacturability.

Key Responsibilities:

  • Develop and Optimize: Create precise layouts for Serdes PHY, analog and mixed-signal ICs, meeting design specifications and ensuring high performance and manufacturability.
  • Collaborate with Design Engineers: Work closely with design engineers to understand design requirements and translate them into layouts.
  • Debugging and Resolution: Strongly experienced in debugging DRC, ERC, LVS, EMIR and PERC issues independently.
  • Integration and Custom Blocks: Collaborate with the physical design team to integrate custom blocks into the overall chip design.
  • Design Reviews and Feedback: Conduct design reviews and provide technical feedback to improve layout practices and methodologies.
  • Industry Trends and Tools: Stay up-to-date with industry trends, tools, and technologies to continuously enhance layout processes.

Qualifications:

  • Experience and Skills: 12-15 years of experience in Serdes Phy, Analog and Mixed-signal IC layout design. Proficiency in layout tools such as Cadence, Synopsys, or Mentor Graphics.
  • Circuit Knowledge: Hands-on experience with custom layout design for various Serdes Phy, Analog and IO circuits, including expertise in Bandgap references, LDOs, Clocking circuits, GPIOs, DDR IOs.
  • Signal Integrity: Familiarity with custom digital layout (i.e. high speed logic paths). Knowledge of signal integrity issues (i.e. clock/data routes, differential routing, shielding).
  • Analog/IO Design: Strong understanding of analog/IO design principles, including circuit performance and parasitic effects.
  • CMOS and FinFET Technologies: Aware of layout techniques to mitigate ESD, latch-up issues. Holds advanced knowledge of CMOS and FinFET technologies and their impact on design and performance issues in deep sub-micron process nodes, specifically 5nm and below.
  • Layout Optimization: Experience with layout concepts that incorporate reliability considerations, including techniques for managing electromigration (EM), IR drop, and self-heating.
  • Problem-Solving: Excellent problem-solving skills and attention to detail.
  • Communication: Effective communication and teamwork abilities.

Preferred Skills:

  • Scripting Languages: Knowledge of scripting languages (e.g., Skill,TCL and SVRF) for automation tasks.

Additional Requirements:

  • Educational Background: Bachelors or Masters degree in Electronics or Electrical Engineering.

At our company, we thrive on the power and potential of diversity. We believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect, and contribution.

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