
Chief Technical Officer of On-Chip Interconnects
7 days ago
The selected candidate will oversee the design of high-bandwidth, low-latency on-chip interconnects (NoC) and chip-to-chip interconnects for high-performance systems. Key responsibilities include designing and architecting different interconnect topologies based on bandwidth, latency, and RAS requirements.
Responsibilities:- Design and architect various interconnect topologies to meet bandwidth, latency, and RAS needs
- Develop features and present proposed architectures in high-level design discussions
- Collaborate with verification, DFT, physical design, FW, and SW teams to develop features
- Sign off pre-silicon designs that meet functional, area, and timing goals
- Participate in silicon bring-up and validation of hardware
- Master's degree in relevant field
- At least 8 years of experience in processor interconnect design delivery leadership
- Expertise in SMP coherency, HDLs (VHDL/Verilog), and queuing theory
- Familiarity with numa/nuca architecture, physical design, and high-speed logic design
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