Static Timing Optimization Engineer

1 week ago

Gandhinagar, Gujarat, India beBeeSeniorTimingExpert Full time ₹ 40,00,000 - ₹ 50,00,000
Job Overview

As a seasoned expert in Static Timing Analysis (STA) and Place and Route (PNR), you will lead STA and PNR activities for complex subsystems, ensuring robust timing closure and physical implementation with a focus on power, performance, and area optimization.

This role involves developing and refining methodologies for STA and PNR tailored to the unique challenges of large, multi-interface, or mixed-signal subsystems.

You will drive automation and validation of timing and physical design data across subsystem boundaries, mentor junior engineers, and collaborate cross-functionally to resolve design, timing, and physical implementation challenges specific to complex subsystem integration.

Key Responsibilities:
  • Lead STA and PNR activities for complex subsystems, ensuring robust timing closure and physical implementation with a focus on power, performance, and area optimization.
  • Develop and refine methodologies for STA and PNR tailored to the unique challenges of large, multi-interface, or mixed-signal subsystems.
  • Drive automation and validation of timing and physical design data across subsystem boundaries.
  • Mentor and guide junior engineers, fostering technical growth and knowledge sharing within subsystem teams.
  • Collaborate cross-functionally to resolve design, timing, and physical implementation challenges specific to complex subsystem integration.
Required Skills and Qualifications:
  • 10+ years of experience in Static Timing Analysis (STA) and Place and Route (PNR) for complex subsystems within ASIC/SoC design, including advanced technology nodes (7nm, or below).
  • Demonstrated expertise in STA tools (e.g., Synopsys PrimeTime, Cadence Tempus) and PNR tools (e.g., Synopsys ICC2, Cadence Innovus) applied to large, multi-block or hierarchical subsystems.
  • Proven track record in timing closure, floorplanning, placement, clock tree synthesis, routing, and physical verification for high-complexity subsystems.
  • Proficient in scripting languages (Tcl, Perl, Python) for automating STA and PNR flows across multiple subsystem blocks.
  • Deep understanding of SoC design flows, with experience collaborating across frontend, physical design, and verification teams to integrate complex subsystems.
  • Experience with IP collateral generation and quality assurance for timing and physical design at the subsystem level preferred.
  • Background in high-speed interfaces, or mixed-signal SoC subsystems.
Benefits:

This role offers the opportunity to work on complex and challenging projects, develop your skills and expertise, and contribute to the success of our team.

Others:

We are an equal opportunities employer and welcome applications from all qualified candidates. Please note that this job description is not exhaustive and you will be required to undertake other duties relevant to the role as necessary.

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