Static Timing Optimization Lead

1 week ago

Vijayawada, Andhra Pradesh, India beBeeTiming Full time ₹ 1,50,00,000 - ₹ 2,00,00,000
Expert Timing Engineer

Job Summary:

Achieve optimal timing closure and physical implementation for complex subsystems by leading STA and PNR activities with a focus on power, performance, and area optimization.

Key Responsibilities:

  • Develop and refine methodologies for STA and PNR tailored to the unique challenges of large, multi-interface, or mixed-signal subsystems.
  • Drive automation and validation of timing and physical design data across subsystem boundaries.
  • Mentor junior engineers, fostering technical growth and knowledge sharing within subsystem teams.
  • Collaborate cross-functionally to resolve design, timing, and physical implementation challenges specific to complex subsystem integration.
  • Present technical solutions and lead discussions with internal teams and customers regarding subsystem-level trade-offs and integration.

Required Skills and Qualifications:

10+ years of experience in Static Timing Analysis (STA) and Place and Route (PNR) for complex subsystems within ASIC/SoC design, including advanced technology nodes (7nm, or below).

Requirements:

  • Expertise in STA tools (e.g., Synopsys PrimeTime, Cadence Tempus) and PNR tools (e.g., Synopsys ICC2, Cadence Innovus) applied to large, multi-block or hierarchical subsystems.
  • Proven track record in timing closure, floorplanning, placement, clock tree synthesis, routing, and physical verification for high-complexity subsystems.
  • Proficient in scripting languages (Tcl, Perl, Python) for automating STA and PNR flows across multiple subsystem blocks.
  • Deep understanding of SoC design flows, with experience collaborating across frontend, physical design, and verification teams to integrate complex subsystems.

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