Highly Skilled ASIC Digital Full-Chip Test Engineer Wanted
1 week ago
Job Summary:
- We are seeking a highly skilled ASIC Digital Full-Chip Test Engineer to join our team.
- The ideal candidate will have extensive experience in DFT design rules and coverages, as well as expertise in test pattern generation using on-chip test compression techniques.
- Solid understanding of ATPG, MBIST verification, and diagnostic tool generation is also required.
- This position requires strong analytical and problem-solving skills, with the ability to work independently and collaboratively within a dynamic environment.
- Excellent communication and interpersonal skills are essential for success in this role.
About the Role:
- DFT Engineer
- Develop and implement high-quality manufacturing ATPG test patterns for stuck-at (SAF) and transition fault (TDF) models.
- Collaborate with ASIC design teams to ensure DFT design rules and coverages are met.
- Work with Product/Test engineering teams on the delivery of manufacturing test patterns for ATE.
- Support post-silicon debug effort, issue resolution, and diagnostic tool generation for ATPG, MBIST, and bring-up on ATE.
- Developing, enhancing, and maintaining scripts as necessary.
Requirements:
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering.
- Minimum of 4 to 12 years' experience in ASIC/DFT - simulation and Silicon validation.
- Should have worked in at least one full chip DFT.
- Detailed knowledge of DFT concepts, pattern simulation, Silicon debug, and yield enhancement.
- In-depth knowledge and hands-on experience in ATPG - coverage analysis.
- In-depth knowledge of Memory verification, repair, and failure root-cause analysis.
- Experience with tools like TestKompress, ETVerify, VCS, ModelSim.
- Expertise in scripting languages such as Perl, shell.
- Ability to work in an international team, dynamic environment with good communication skills.
- Ability to learn and adapt to new tools, methodologies.
- Ability to do multi-tasking & work on several high-priority designs in parallel.
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