High Performance CPU Verification Specialist

7 hours ago


Delhi, Delhi, India Tenstorrent Full time

The Tenstorrent team is a unique blend of technologists from diverse disciplines united by their passion for AI and commitment to delivering exceptional products.

We prioritize collaboration, curiosity, and innovative problem-solving. Learn more about our company culture.

Job DescriptionL2/Shared Cache Verification Expertise

An experienced engineer will be responsible for verifying high-performance CPUs' L2/Shared Cache units, working closely with Architecture and RTL teams.

  • Develop comprehensive verification plans for the L2/Shared Cache unit, encompassing architectural (RISCV ISA) and microarchitectural functionality.
  • Design and implement reusable block-level testbench components in SV, UVM, and C++, including microarchitectural models, monitors, and checkers.
  • Create random and directed stimulus spanning pre-silicon, emulation, and post-silicon domains.
  • Evaluate and integrate open-source toolchains into the DV flow.
  • Develop a DV environment, tools, and infrastructure to facilitate functional verification across pre-silicon, emulation, and post-silicon phases.
  • Collaborate with design, test, and post-silicon validation teams to ensure high-quality delivery of the L2/Shared Cache block.
RequirementsQualifications and Experience

A BS/MS/PhD in EE/ECE/CE/CS with at least 7 years of experience is required.

  • Strong background in high-performance OOO CPU microarchitecture, particularly with load/store, caches, and memory subsystems.
  • Experience working on x86, ARM, or RISCV-based CPUs is desirable.
  • Architectural understanding of address translation, memory ordering, cache coherence protocols, memory consistency, multi-processors, and fabric topologies.
  • Significant experience debugging RTL and DV in simulation environments.
  • Verification methodologies and techniques – simulation/debug, TB development, stimulus, checking, coverage, infrastructure, and tools.
  • Experience with C++/SV/UVM and scripting languages.
  • Familiarity with hardware description languages (Verilog, VHDL) and simulators (VCS, NC, Verilator).
  • Strong problem-solving and debugging skills across various design hierarchies.

Estimated Salary: $120,000 - $180,000 per year



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