Senior Digital Design Engineer for Timing Analysis

4 days ago

Bengaluru, Karnataka, India beBeeDigitalDesignEngineer Full time ₹ 12,00,000 - ₹ 25,00,000

Job Summary

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We are seeking a seasoned Senior Digital Design Engineer to lead our efforts in Static Timing Analysis (STA). As part of our elite team, you will be responsible for defining and driving cutting-edge features and solutions using Cadence's Tempus Timing Signoff platform.

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Your primary focus will be on advancing signoff-level accuracy and performance across real-world System-on-Chip (SoC) designs. You will collaborate closely with research and development teams, customers, and field engineers to ensure seamless integration and adoption of our STA solutions.

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Main Responsibilities

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  • Advanced STA Deployment:">
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    • Drive the adoption and support of Cadence's Tempus tool in advanced timing closure and signoff flows.">
    • Perform comprehensive STA using SDC constraints, Place and Route (PBA/GBA) methodologies, and advanced ECO flows.">
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  • Design Enablement & Ecosystem Integration:">
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    • Define and enable use cases that integrate Tempus with synthesis, place and route, IR drop, and Electromagnetic (EM) analysis flows.">
    • Collaborate with design teams to ensure end-to-end timing convergence at advanced nodes (5nm, 3nm, and below).">
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  • Feature Specification & Roadmap Contribution:">
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    • Gather and analyze customer requirements and translate them into robust, production-ready product specifications.">
    • Propose enhancements and new feature ideas to improve timing analysis accuracy, runtime, and usability.">
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  • Debug & Validation Expertise:">
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    • Reproduce and debug complex timing scenarios including On-Chip Variation (OCV), Critical Race Path Reduction (CRPR), path-based analysis, and clock-domain crossings.">
    • Develop validation flows for STA features using industry benchmarks and regression testing.">
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  • Collaboration:">
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    • Work closely with R&D, application engineers, and field Application Engineers to validate new capabilities and improve customer satisfaction.">
    • Provide technical training, best practices, and documentation to internal teams and end users.">
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Required Skills & Qualifications

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  • A strong background in digital design and static timing analysis.">
  • Expertise in Electronic Design Automation (EDA) tool usage, specifically Tempus, PrimeTime, or similar STA tools.">
  • A deep understanding of:">
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    • Timing constraints (SDC), Clock Tree Synthesis, ECO closure">
    • Multi-mode multi-corner (MMMC) analysis">
    • On-chip variation (AOCV/POCV), derating, and margin analysis">
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  • Proficiency in TCL, Python, and scripting for tool automation and debugging.">
  • Familiarity with RTL-GDSII design flow, synthesis, place and route, and Design Rule Check (DRC)/Layout Versus Schematic (LVS) signoff.">
  • Experience working with advanced process nodes (FinFET/GAA) is a plus.">
  • Excellent communication, problem-solving, and cross-functional collaboration skills.">
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Educational Qualification

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  • Bachelor's/Master's degree in Computer Engineering from a reputable institution.">
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About Us

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We are committed to innovation and excellence in the field of digital design and Static Timing Analysis. Our team is passionate about pushing boundaries and delivering cutting-edge solutions to meet the ever-evolving needs of our customers.

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What We Offer

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We offer a dynamic work environment, opportunities for growth and professional development, and a competitive compensation package.

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