Chief Digital Fault Tolerance Architect

3 days ago

Tirupati, Andhra Pradesh, India beBeeDftEngineer Full time ₹ 15,00,000 - ₹ 25,00,000

Job Title: Lead DFT Engineer

Experience: 7+ Years

Location: Global Opportunity

Employment Type: Full-time

Industry: Semiconductors / ASIC / SoC Design

Job Summary:

We are seeking a skilled engineer to lead the development of Digital Fault Tolerance architecture, planning, and implementation across complex SoC/ASIC designs.

Key Responsibilities:

  • Define and drive DFT strategy and architecture for multiple ASIC/SoC projects.
  • Implement and verify DFT features like scan insertion and compression (e.g., EDT), ATPG pattern generation and fault grading, MBIST and Logic BIST insertion and validation, boundary scan (IEEE 1149.1/1149.6), IJTAG (1687).
  • Manage end-to-end DFT flow from RTL to gate-level netlist and silicon bring-up.
  • Collaborate with RTL, STA, PD, and test engineering teams for seamless integration.
  • Perform pattern generation, fault simulation, and debug test coverage gaps.
  • Own DFT signoff, timing closure (DFT-related paths), and ATE pattern delivery.
  • Support silicon bring-up, test vector validation on ATE, and yield optimization.
  • Mentor and guide junior engineers; conduct design reviews and training sessions.
  • Develop and maintain DFT automation scripts and infrastructure.

Required Skills and Qualifications:

  • B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design.
  • 7+ years of experience in DFT for complex ASIC or SoC designs.
  • Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.
  • Hands-on experience with DFT tools such as Synopsys: DFT Compiler, TetraMAX, TestMAX, Siemens EDA: Tessent ScanPro, MBIST, IJTAG, Cadence/others: Modus, Encounter Test.
  • Strong knowledge of RTL design, STA, and synthesis flows.
  • Proficient in scripting languages (Python, Perl, Tcl) for flow automation.
  • Deep understanding of silicon test challenges and test coverage improvement.
  • Strong leadership, team collaboration, and communication skills.

Preferred Qualifications:

  • Experience with hierarchical DFT and low-power DFT methodologies (UPF).
  • Exposure to post-silicon validation and failure analysis.
  • Familiarity with safety-critical designs (ISO 26262) and functional safety.
  • Experience working in advanced nodes (e.g., 7nm, 5nm, FinFET).

Why this Role is Unbeatable:

  • Drive DFT for high-performance, next-gen SoCs and ASICs.
  • Collaborate with top-tier engineers and global semiconductor leaders.
  • Fast-track growth opportunities.

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