Senior Chip Design Engineering Lead
3 days ago
We are seeking an experienced Physical Design Manager to lead our team in delivering the next generation of cutting-edge designs.
About the Role- Manage a team of 10+ engineers responsible for Synthesis, Physical Design, timing and Physical closure
- Oversee a large team of internal and external resources to ensure timely completion of the SOC chip with high QOR
Key Responsibilities:
- Physical implementation of block level and subsystem level
- Contribute to Synthesis, Power Reduction, Timing Convergence Floorplan efforts of block and subsystem
- Proven track record of successfully managing PD teams for complex SOCs
- In-depth understanding and experience of all Physical Design activities for a large, leading technology SOC ASIC chip
- Strong management, technical problem-solving, communication, and presentation skills
PREFERRED EXPERIENCE:
- Excellent team player able to effectively interact and collaborate with partner teams
- Experience with Front-End design, DFX and Physical Design Flows
- Communication skills: excellent oral, written, and presentation skills
Technical Skills:
- Extensive experience in handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk
- Hands-on experience on 7nm and sub-7nm projects
- Experienced in Full Chip Floorplanning, PNR Partitioning / Bump Placement is preferred
Academic Credentials:
- BE/B.Tech/ME/M.TECH or equivalent ECE/EEE degree
Salary: Estimated annual salary $180,000-$220,000 depending on experience and qualifications
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