Principal Architect

2 weeks ago

Kottayam, Kerala, India beBeeLogic Full time ₹ 1,50,00,000 - ₹ 2,00,00,000
Job Overview

We are seeking a seasoned Hardware Developer to join our team. This individual will be responsible for architecting and designing processor core front-end pipeline units for high-performance systems.

This is an exciting opportunity to work on cutting-edge technology and be part of a talented engineering team that enables customers to make informed decisions with the most trusted hardware platform in the market.

Responsibilities
  1. Lead the architecture, design, and development of Processor Core Front-end pipeline units for high-performance Systems.
  2. Architect and design I-Cache, Instruction Fetch, Branch Prediction, and Decode units of a high-performance processor CPU.
  3. Develop the features, present the proposed architecture in high-level design discussions.
  4. Estimate the overall effort to develop the feature.
  5. Estimate silicon area and wire usage for the feature.
  6. Develop micro-architecture, design RTL, collaborate with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature.
  7. Signoff the Pre-silicon Design that meets all functional, area, and timing goals.
  8. Participate in post-silicon lab bring-up and validation of the hardware.
  9. Guide and mentor team members, represent as Logic Design Lead in global forums.
Requirements
  • Doctorate Degree.
  • 8 or more years of demonstrated experience in architecting and designing specific CPU unit (eg. I-Cache, Instruction Fetch, Branch Prediction, Instruction Decode).
  • Hands-on experience of different Branch Prediction techniques.
  • Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA.
  • Experience with high-frequency, instruction pipeline designs.
  • At least 1 generation of Processor Core silicon bring-up experience.
  • In-depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs).
  • Proficiency in RTL design with Verilog or VHDL.
  • Knowledge of at least one object-oriented or functional programming language and scripting language.
Nice to Haves
  • Knowledge of instruction decode and handling pipeline hazards.
  • Knowledge of verification principles and coverage.
  • High-level knowledge of Linux operating system.
  • Understanding of Agile development processes.
  • Experience with DevOps design methodologies and tools Required.

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