
Senior Memory Design Specialist
21 hours ago
The ideal candidate will be responsible for developing memory compilers and memory Fast Cache instances for our next generation Cores, achieving outstanding Performance, Power, and Area (PPA) metrics.
Key Responsibilities:
- Developing high-performance and low-power circuit designs with exposure to FinFet technologies
- Leading a small team of designers in the development of memory blocks such as SRAM, register files, and caches
- Designing and developing digital circuits for memory blocks
- Performing simulations and verification to ensure functionality and optimize for power, performance, area, timing, and yield
Requirements:
- Minimum 7 years of experience in SRAM/memory design margin, char, and quality checks
- Strong knowledge of physical implementation impact on circuit performance
- Good understanding of computer architecture and concepts
- Good experience in design verification: sense amplifier analysis, self-time analysis, and marginality analysis
- Understanding of high-speed/low-power CMOS circuit design, clocking scheme, static, and complex logic circuits
- Understanding of power versus performance versus area trade-offs in typical CMOS design
Nice to Have Skills and Experience:
- Some experience working on Cadence or Synopsys flows
- Experience with circuit simulation and optimization of standard cells
What We Offer:
- Opportunity to work on cutting-edge technology
- Collaborative and dynamic work environment
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