Principal Verification Engineer
2 weeks ago
As a Principal Verification Engineer at Analog Devices, you will lead the verification effort for complex digital SOCs, ensuring end-to-end verification responsibility. You will work closely with design and architecture teams to define requirements and coordinate verification deliverables and receivables.
Key Responsibilities- Lead SOC verification for complex digital SOCs
- Verify complex microprocessor designs, neural nets, and high-speed peripherals using advanced verification methodologies
- Define tasks for team members, coordinate team effort, and track progress
- Work with emulation, system FPGA, and software teams to define post-silicon validation requirements
- Identify, code, and validate end-to-end system use case scenarios
- Develop and implement UVM testbench architecture and DV flows
- Define test plans, tests, and verification methodology for block/subsystem and chip-level verification
- Work with design teams to generate and review test plans and closure of code and functional coverage
- Collaborate with other verification team disciplines to determine correct functionality
- Formally verify IPs and subsystems
- B.Tech/M.Tech with 12+ years of industry experience in digital pre-silicon verification
- Experience in leading IP, subsystem, or SOC-level verification
- Good understanding of SOC/subsystem design concepts and design architectures
- Hands-on experience in developing, updating, and debugging Verilog, SV-UVM, and SOC-level testbenches
- Experience in closing verification of block, subsystem-level verification using industry-standard metrics
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