Principal Engineer

1 month ago

Bengaluru, Karnataka, India Analog Devices Full time
Job Title: Principal Engineer - Design Verification

We are seeking a highly skilled Principal Engineer to lead our Design Verification team in the development of complex digital SOCs. As a key member of our team, you will be responsible for the end-to-end verification of SOC designs, including the development of verification plans, testbenches, and methodologies.

Key Responsibilities:
  • Lead the SOC verification team to ensure timely and successful completion of verification tasks
  • Develop and implement verification plans, testbenches, and methodologies for complex SOC designs
  • Collaborate with design and architecture teams to define requirements and coordinate verification deliverables and receivables
  • Work with emulation, system FPGA, and software teams to define post-silicon validation requirements and intercept all post-silicon requirements in pre-silicon verification
  • Identify, code, and validate end-to-end system use case scenarios
  • Develop and implement UVM testbench architectures and DV flows
  • Define test plans, tests, and verification methodologies for block/subsystem and chip-level verification
  • Collaborate with other verification team disciplines to determine correct functionality
  • Formal verification of IPs and subsystems
  • NOC, interconnect verification
  • Performance verification and performance analysis of complex SOCs end-to-end scenarios
  • System-level use case scenarios definition, coding, and verification
  • Innovate verification solutions to hit deliverable schedules
  • Exposure to and learning of state-of-the-art verification techniques such as formal, emulation, portable stimulus, and virtual platforms
  • Development of verification strategies for products after going through product requirements and design specifications
Requirements:
  • B.Tech/M.Tech with 12+ years of industry experience in digital pre-silicon verification
  • Experience in leading IP, subsystem, or SOC-level verification
  • Good understanding of SOC/subsystem design concepts and design architectures
  • Hands-on experience in developing, updating, and debugging Verilog, SV-UVM, and SOC-level testbenches
  • Experience in closing verification of block, subsystem-level verification using industry-standard metrics like code and functional coverage
  • Expertise on NOC, bus, and interconnect verification, coverage analysis, and improvements
  • Test bench, TB, environment, architect, and implement verification flow and methodology
  • Power-aware verification with UPF, power analysis, and power optimization
  • Formal verification, define formal verification flow, connectivity, and functional verification using formal tools
  • Gate-level simulation with timing-annotated
  • Strong knowledge of test-plan generation, coverage analysis, transaction-level modeling, pseudo, and constrained random techniques with System Verilog
  • In-depth knowledge of SV-UVM and debugging of testbenches
  • Assertion and formal knowledge is an advantage
  • Knowledge of microprocessor cores such as ARM, RISC-V, Tensilica, neural network, GPU cores is a plus
  • System Verilog, C/C++, System C, TCL/Python/shell-scripting
  • Experience in analog and mix-signal verification (ADC/DAC/PLL/Sensors/PHY) is an added advantage
  • Exceptional interpersonal and communication skills, collaborate, and influence innovative design development/verification methodologies to a wider team spread across the globe
  • Quick to adopt new technologies with good problem-solving skills

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