ASIC Design Engineer for Timing Closure and DFT Expertise
7 days ago
Job Description:
Samsung Semiconductor India Research (SSIR) is seeking a skilled ASIC design engineer with exceptional analytical and technical abilities to participate in the development of high-speed designs. This role focuses on designing and implementing Digital Fault Tolerance (DFT) strategies, ensuring timely closure and efficient testing.
Key Responsibilities:
- Design and implement top-level test pin planning, ATPG partitioning, MBIST planning, and optimization
- Architect DFT clocking schemes, EFUSE planning for memory repair, and define scan compression
- Analyze low coverage and improve test coverage for various fault models
- Generate patterns, simulate with SDF, and verify results
- Work with cross-functional teams to achieve timing closure in DFT modes
Requirements:
- Proven experience in top/block, flat/hier DFT insertion flow methodologies
- Expertise in scan and MBIST insertion, ATPG, and verification at full chip level
- Understanding of shift, capture timing constraints, MBIST constraints, and their impacts on timing closure
- Ability to generate, review, and validate DFT constraints to achieve timing closure in high-speed designs
- Experience in RTL analysis, logic synthesis, physical design, signoff verification (STA, Formality, Simulations)
- Knowledge of analog and mixed signal IP tests, such as PLLs and MIPI, including pattern generation and verification
- Exposure to post-silicon bring-up, diagnosis, and debug methods to identify fail points for logic or memory tests
- Self-driven, adaptable, flexible, creative, and capable of working independently
- Strong written and oral communication skills
- Good understanding of Deep Sub Micron topics and their associated issues
Preferred Qualifications:
- Experience in Power Estimation/Management for DFT modes
- Able to mentor juniors, support periodic training sessions, and work with teams across sites
Salary Estimate: ₹30-50 lakhs per annum based on experience and qualifications
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