Senior ASIC Synthesis and Timing Closure Specialist
4 days ago
We are seeking an experienced Senior ASIC Synthesis and Timing Closure Specialist to join our team at SignOff Semiconductors.
About the Role:
- The ideal candidate will be responsible for the front-end implementation of IPs, including synthesis, LEC, CLP, pre-layout STA, and post-layout STA/timing closure.
- Collaboration with design teams and PNR teams is essential to achieve timing closure.
- The selected individual must have strong planning and organizational skills to understand duration requirements and execute tasks accordingly.
- They will also be expected to deliver high-quality results in synthesis and timing closure.
- Debugging and resolving technical issues will be a key responsibility.
Requirements:
- Possess extensive experience in synthesis, LEC, CLP, and timing closure.
- A preference for top-level or SOC-level experience is advantageous.
- The ideal candidate should have handled blocks with complex designs, high-frequency clocks, and complex clocking.
- Complete understanding of timing constraints, low-power aspects, and DFT concepts is crucial.
- Able to debug and resolve technical issues efficiently.
- Proficiency in scripting and automation is required.
- A minimum of 4+ years of relevant experience is necessary.
Compensation:
The estimated salary for this role is $120,000 - $180,000 per annum, depending on qualifications and location. We offer a competitive compensation package that includes benefits such as health insurance, retirement plans, and paid time off.
About Us:
At SignOff Semiconductors, we strive to provide innovative semiconductor solutions that drive technological advancements. Our company culture values teamwork, innovation, and continuous learning. If you are a motivated and experienced professional looking for a new challenge, we encourage you to apply for this exciting opportunity.
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