Digital Verification Expert

7 days ago

Bengaluru, Karnataka, India beBeeVerification Full time ₹ 80,00,000 - ₹ 1,50,00,000
Key Position Overview:

We are seeking an experienced Senior Verification Engineer to join our team. In this role, you will be responsible for leading the development of complex digital systems.

Job Description:

The ideal candidate will have a strong background in digital verification methodologies, along with specialization in one or more of the following areas: processor/microarchitecture verification, high-speed interfaces (e.g., PCIe, USB, DDR), or Gate-Level Simulation.

  • Develop and execute detailed verification plans for digital blocks, subsystems, or systems.
  • Design and build SystemVerilog/UVM-based testbenches, scoreboards, monitors, and drivers.
  • Write and maintain directed and constrained-random test cases.
  • Perform Gate-Level Simulation with SDF back-annotation, reset validation, scan chain checking, and X-propagation analysis.
  • Verify processor cores or custom pipelines, including cache/memory subsystems, MMUs, and coherency.
  • Validate high-speed protocols (e.g., PCIe Gen4/Gen5, USB 3.x, DDR3/4/5, LPDDR, CXL).
  • Debug RTL and testbench issues using waveforms, logs, and assertions.
  • Collaborate with RTL, DFT, STA, firmware, and post-silicon teams to drive quality and coverage closure.
  • Analyze functional/code/line/branch/coverage metrics and drive closure.
  • Automate regressions and result analysis using scripting languages (Python, Perl, Shell, Tcl).
Requirements:
  • Bachelor's/Master's degree in Electronics, Electrical, or Computer Engineering.
  • 5–15 years of experience in digital system verification.
  • Expertise in SystemVerilog, UVM, and constrained-random verification.
  • Hands-on experience with simulation tools: VCS, Xcelium, Questa, Verdi, etc.
  • Proven track record in processor/microarchitecture verification, high-speed protocol verification, or Gate-Level Simulation.
  • Strong debugging skills and understanding of design specs and verification architecture.
  • Proficient in scripting (Python, Perl, Shell, or Tcl) for test automation.
  • Familiar with DFT/scan concepts, low power (UPF), and assertion-based verification (SVA).
Preferred Qualifications:
  • Experience in ARM-based SoCs or RISC-V CPU verification.
  • Exposure to formal verification, LEC, or static verification tools.
  • Knowledge of post-silicon validation, FPGA prototyping, or emulation.
  • Experience leading small teams or mentoring junior engineers.

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