
High-Performance Memory Design Engineer-SRAM
2 days ago
**Job Opportunity: Memory Design Engineer-SRAM**
We are seeking an experienced Memory Design Engineer-SRAM to join our team. As a key member of our design team, you will be responsible for designing and verifying complex SRAM memory cells and arrays.
The ideal candidate will have over 8 years of experience in full-custom memory design and architectures, including characterization, layout design, net-listers, and SRAM design verification at the compiler level.
A strong understanding of different memory architectures is essential, along with hands-on experience designing SRAM leafcells from scratch to top-level integration.
The person should be proficient in various physical verification flows, such as DRC, LVS, DFM, PERC, ERC, EM, and IR.
Cadence Virtuoso layout editor and Caliber Physical Verification flow expertise are a must.
Synopsys Custom Compiler experience is highly desirable.
The individual should also have a solid understanding of good layout practices for lower process nodes and experience working on FinFET architecture and challenges like variability and manufacturability.
The successful candidate will create detailed and optimized physical layouts for memory cells, arrays, and peripheral circuits using tools like Cadence Virtuoso or Synopsys Custom Compiler.
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