Senior Hardware Validator

2 days ago

Cochin, Kerala, India beBeeVerification Full time ₹ 1,50,00,000 - ₹ 2,50,00,000

Job Title: Senior Design Verification Engineer

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About the Role:

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  • We are seeking a skilled Senior Design Verification Engineer to develop and execute detailed verification plans for IP blocks, subsystems, or SoCs.">
  • The ideal candidate will have expertise in SystemVerilog, UVM, and constrained-random verification, as well as hands-on experience with simulation tools such as VCS, Xcelium, Questa, Verdi, etc.">
  • This is an exciting opportunity for someone who wants to drive quality and coverage closure, collaborate with cross-functional teams, and contribute to methodology improvements.">
  • As a Senior Design Verification Engineer, you will be responsible for developing and executing testbenches, writing and maintaining test cases, performing GLS (Gate-Level Simulation), and debugging RTL and testbench issues.">
  • You will also analyze functional/code/line/branch/coverage metrics and automate regressions using scripting languages like Python, Perl, Shell, Tcl.">
  • This role requires strong problem-solving skills, attention to detail, and excellent communication skills.">
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Required Skills & Qualifications:

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  • B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or Computer Engineering.">
  • 5–15 years of experience in ASIC/IP/SoC/Processor Design Verification.">
  • Expertise in SystemVerilog, UVM, and constrained-random verification.">
  • Hands-on experience with simulation tools: VCS, Xcelium, Questa, Verdi, etc.">
  • Proven track record in any one or more of the following:">
  • Processor/Microarchitecture Verification (pipelines, instruction decode, coherency, etc.)">
  • High-speed Protocol Verification (PCIe, DDR, USB, Ethernet, CXL, etc.)">
  • GLS Verification (Zero-delay and SDF annotated simulations, scan chain checks, X-handling)">
  • Familiar with DFT/scan concepts, low power (UPF), and assertion-based verification (SVA).">
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Good to Have:

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  • Experience in ARM-based SoCs or RISC-V CPU verification.">
  • Exposure to formal verification, LEC, or static verification tools.">
  • Knowledge of post-silicon validation, FPGA prototyping, or emulation.">
  • Experience leading small teams or mentoring junior engineers.">

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