
Advanced Mixed-Signal Chip Engineer
4 days ago
As a senior ASIC STA engineer, you will be responsible for leading the synthesis and static timing analysis efforts for an advanced mixed-signal chip. This is a highly visible role that requires expertise in STA tools, methodologies, and timing closure.
Key responsibilities include full chip and block level timing closure ownership, developing and maintaining methodology and flows related to timing verification and closure, generation of block and full chip timing constraints, and analyzing timing reports using scripting techniques.
Required Skills and QualificationsThe ideal candidate will have a strong understanding of ASIC design timing constraints generation and timing closure, as well as expertise in STA tools such as Tempus and Primetime. Familiarity with low-power techniques, including clock gating, power gating, and millivoltage designs, is also necessary. Additionally, the candidate should have strong communication skills and be able to work independently under limited supervision.
- BTech/MTech/PhD degree with at least 6+ years hands-on experience in ASIC timing constraints generation and timing closure
- Expertise in STA tools (Tempus and Primetime) and methodologies for timing closure with a good understanding of OCV, noise, and crosstalk effects on timing
- Familiarity with all aspects of timing closure of high-performance, mixed-signal SoCs in advanced finFET technology nodes, preferably 7nm
This role offers a competitive compensation package, medical benefits, and opportunities for career development and growth. You will be working on leading-edge technologies and collaborating with a talented team to deliver cutting-edge solutions.
Other OpportunitiesWe are looking for a motivated and skilled individual who can drive complex projects to completion. If you have a passion for solving problems and delivering results, this could be the perfect opportunity for you.
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