Lead Analog Layout Optimization Engineer

3 days ago

Hyderabad, Telangana, India beBeeOptimization Full time ₹ 9,00,000 - ₹ 12,00,000

Expert analog layout design professionals are sought after to collaborate with our team in cutting-edge projects. The ideal candidate has 5–12 years of experience working on TSMC technology nodes, preferably 5nm and 7nm.


Locations:
Hyd

Notice Period:
Immediate - 30 days or Less Preferred

Key Responsibilities:
We require highly skilled engineers with a strong background in analog layout optimization, including IR drop, electromigration, self-heating, RC delay, and parasitic capacitance optimization.
  • Implement layouts that meet tight design constraints and deliver high-quality results.

A solid understanding of how layout impacts circuit performance (speed, area, etc.) is essential.

Proficiency in CADENCE/SYNOPSYS layout tools and flows is necessary.

Familiarity with scripting languages like PERL/SKILL is an advantage.

Effective communication skills and experience working with cross-functional teams are required.


Interested individuals can send their updated resumes for consideration.

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