Senior Analog Layout Engineer
4 weeks ago
Greetings from Eximietas Design
We are actively looking to hire Senior Analog Layout Design Engineers / Leads with (TSMC 5nm) 5–12 years of experience to join our growing team.
Locations: Hyderabad.
Notice Period: Immediate - 30 days or Less Preferred
Job Description:
We're seeking highly skilled professionals with a strong background in lower FINFET technology nodes (TSMC 5nm/7nm preferred) to contribute to cutting-edge analog layout design.
Key Skills & Requirements:
Expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization.
Solid understanding of how layout impacts circuit performance (speed, area, etc.).
Ability to implement layouts that meet tight design constraints and deliver high quality.
Hands-on experience with CADENCE/SYNOPSYS layout tools and flows.
Familiarity with scripting languages (PERL/SKILL) is a plus.
Strong communication skills and experience working with cross-functional teams.
If this opportunity interests you—or if you know someone suitable—please send your updated resume to:
Referrals are highly appreciated.
We look forward to connecting with talented engineers passionate about pushing the boundaries of analog layout design
Maruthhi Naidu
Talent Associate - VLSI Manager
Eximietas Design - Visakhapatnam
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