Senior Architectural Designer

18 hours ago

Bareilly, Uttar Pradesh, India beBeeEngineer Full time ₹ 1,75,00,000 - ₹ 2,61,00,000

Silicon Labs is not mentioned in this job post, but we are looking for a Senior Staff Engineer to join our team.

This position involves the development of complex architectures with multi-core, multi-threaded processor subsystems, AI accelerators, interconnects, memory architecture and multi-level caches, multiple clocks and resets, high-speed interfaces, peripherals.

The chosen candidate would need to contribute to, and manage a team for, the development of architectures, microarchitectures, and designs of SoCs which include RISC-V, ARM or proprietary processor designs, and high-speed interfaces for off-chip memories, along with the integration of wireless systems, power management, and mixed signal IP.

Key Responsibilities:

  • Lead the development and execution of Wireless SoC's from definition, through execution, and into production
  • Coordinate with product marketing teams to develop SoC requirements. Provide necessary design collateral to support product approval gates.
  • Develop and maintain SoC architecture or technical specification to meet product requirements, with a key goal to maximize IP reuse.
  • Develop the design schedule, including milestones and resource requirements. Coordinate with cross-functional teams (such as software) on dependencies.

Requirements:

  • 12+ years of industry experience
  • Bachelor or Master's degree in Electrical or Computer Engineering
  • Capable of leading complex IP, SOC development projects execution. Experience coordinating with contractors a plus.
  • Top-down planning and execution of SOC projects.
  • Experience in full-chip development cycle
  • Able to build strong technical team.
  • Hands-on experience in architecture, micro-architecture, digital design processes
  • Knowledge of high-speed interfaces like USB, PCIe, Ethernet, Mobile DDR, Quad/Octa-SPI
  • Knowledge of processors like RISC-V and ARM processors
  • Knowledge of design signoff flows including Lint, CDC, Formal Verification, Synthesis, Constraints and STA Timing Closure
  • Knowledge of DFT including Scan, ATPG, MBIST
  • Knowledge of low power design methodology (static/dynamic clock gating, power gating, dynamic voltage and frequency scaling)
  • Knowledge of hardware accelerators
  • Knowledge of Verilog and System Verilog
  • Knowledge of scripting languages like Perl, Python, Tcl, shell

Benefits & Perks :

  • Equity Rewards (RSUs)
  • Employee Stock Purchase Plan (ESPP)
  • Insurance plans with Outpatient cover
  • National Pension Scheme (NPS)
  • Flexible work policy
  • Childcare support

We strive for good work/life balance and to make our environment welcoming and fun.

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