Principal Design Engineering Lead

6 hours ago


Salem, Tamil Nadu, India beBeeEngineer Full time ₹ 16,89,600 - ₹ 30,19,520

Job Overview

  • We are seeking a seasoned RTL Principal Design Engineer to lead the design and development of high-performance IP solutions for Cadence.

About This Role

  • This is an exceptional opportunity for a skilled engineer with extensive experience in RTL design, system verilog, and UVM based environment usage/debugging to contribute to our cutting-edge projects.
  • You will be working closely with cross-functional teams to design, test, and deliver complex RTL designs that meet customer requirements.

Your Responsibilities

  • Design and develop high-quality RTL code for IP solutions using Verilog.
  • Collaborate with engineers to add new features, ensure customer configurations are clean, and provide support for design verification against LINT and CDC guidelines.
  • Work on existing RTL code, adding new functionality, and implementing complex protocols such as PCIe/CXL/IDE.
  • Develop and maintain documentation for RTL designs, ensuring accuracy and clarity.

Requirements

  • Bachelor's degree in Electrical/Electronics/VLSI engineering or related field with at least 8-16 years of core RTL Design experience.
  • Expertise in System Verilog and UVM based environment usage/debugging required.
  • Prior experience in IP development teams and knowledge of scripting beneficial.

Bonus Points

  • PCIe/CXL/IDE experience and prior implementation of complex protocols highly desired.


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