Advanced DFT Architect

2 days ago

Shimoga, Karnataka, India beBeeDft Full time ₹ 15,00,000 - ₹ 25,00,000
Lead DFT Architect Position

We are seeking a skilled Lead DFT Architect to drive the development and implementation of advanced DFT architectures for complex SoC/ASIC designs. The ideal candidate will have expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.

The successful candidate will be responsible for defining and driving DFT strategy and architecture across multiple projects, managing the end-to-end DFT flow from RTL to gate-level netlist, and collaborating with cross-functional teams.

  • Define and drive DFT strategy and architecture for multiple ASIC/SoC projects.
  • Implement and verify DFT features like scan insertion and compression (e.g., EDT), ATPG pattern generation and fault grading, MBIST and Logic BIST insertion and validation, boundary scan (IEEE 1149.1/1149.6), IJTAG (1687).
  • Manage end-to-end DFT flow from RTL to gate-level netlist and silicon bring-up.
  • Collaborate with RTL, STA, PD, and test engineering teams for seamless integration.
  • Perform pattern generation, fault simulation, and debug test coverage gaps.
  • Own DFT signoff, timing closure (DFT-related paths), and ATE pattern delivery.

Required Skills:

  • B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design.
  • 7+ years of experience in DFT for complex ASIC or SoC designs.
  • Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.
  • Hands-on experience with DFT tools such as Synopsys: DFT Compiler, TetraMAX, TestMAX, Siemens EDA: Tessent ScanPro, MBIST, IJTAG, Cadence/others: Modus, Encounter Test.
  • Strong knowledge of RTL design, STA, and synthesis flows.

Preferred Qualifications:

  • Experience with hierarchical DFT and low-power DFT methodologies (UPF).
  • Exposure to post-silicon validation and failure analysis.

This role offers an exciting opportunity to work on cutting-edge DFT technologies and collaborate with a talented team of engineers.

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