Design for Test Engineer
7 days ago
Key Responsibilities and Accountabilities
We are seeking a highly motivated and skilled DFT engineer to join our team. The successful candidate will be responsible for designing and implementing DFT architecture for complex SoCs.
The ideal candidate should have strong expertise in DFT architectures and methodologies, including but not limited to:
- Scan Insertion & Verification
- ATPG (Automatic Test Pattern Generation)
- MBIST (Memory Built-In Self-Test)
- JTAG / Boundary Scan
The candidate should also have hands-on experience with industry-standard DFT tools and methodologies from Cadence, Synopsys, and Mentor Graphics (Siemens EDA).
Additionally, the successful candidate should have proven ability to develop and debug scripting solutions using Python, Perl, and TCL for automation of DFT flows.
Benefits and Opportunities
The role offers a range of benefits and opportunities, including:
- Collaboration with experienced engineers and technical experts
- Professional development and training opportunities
- A competitive salary and bonus structure
Requirements
To be considered for this exciting opportunity, you should have:
- Strong expertise in DFT architectures and methodologies
- Hands-on experience with industry-standard DFT tools and methodologies
- Proven ability to develop and debug scripting solutions using Python, Perl, and TCL
Preferred Skills
Prior experience working with low-power DFT techniques, post-silicon bring-up, and safety-critical standards is desirable but not essential.
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