Chief Digital Fault Tolerance Architect

23 hours ago

Bareilly, Uttar Pradesh, India beBeedftengineer Full time ₹ 2,16,00,000 - ₹ 2,88,60,000
Job Description

We are seeking a seasoned Digital Fault Tolerance (DFT) expert to lead our DFT architecture, planning, and implementation efforts across complex SoC/ASIC designs.

The ideal candidate has a strong background in DFT for complex ASIC or SoC designs, with expertise in scan insertion, compression, ATPG, MBIST, and boundary scan. Proficiency in scripting languages (Python, Perl, Tcl) for flow automation is also necessary.

Key Responsibilities:

  • Define and drive DFT strategy and architecture for multiple ASIC/SoC projects.
  • Implement and verify DFT features like scan insertion and compression, ATPG pattern generation and fault grading, MBIST and Logic BIST insertion and validation, boundary scan, and IJTAG.
  • Collaborate with cross-functional teams to ensure world-class testability and manufacturability of silicon products.

Required Skills and Experience:

  • B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design.
  • 7+ years of experience in DFT for complex ASIC or SoC designs.
  • Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.
  • Hands-on experience with DFT tools such as Synopsys: DFT Compiler, TetraMAX, TestMAX, Siemens EDA: Tessent ScanPro, MBIST, IJTAG, Cadence/others: Modus, Encounter Test.

Benefits:

  • Opportunity to work on cutting-edge technology and innovative products.
  • Collaborative and dynamic work environment.
  • Ongoing training and professional development opportunities.

Preferred Qualifications:

  • Experience with hierarchical DFT and low-power DFT methodologies (UPF).
  • Exposure to post-silicon validation and failure analysis.
  • Familiarity with safety-critical designs (ISO 26262) and functional safety.
  • Experience working in advanced nodes (e.g., 7nm, 5nm, FinFET).

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