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2 days ago
The role involves designing and implementing digital fault tolerance (DFT) strategies for semiconductor devices. This includes developing comprehensive plans, collaborating with cross-functional teams, and architecting solutions for scan and built-in self-test circuitry.
Key Responsibilities:- Responsible for scan insertion and validation, BIST, MBIST insertion and validation, ATPG, IP tests and pattern validation with/without timing, DFT mode timing analysis and sign-off.
- Develop a comprehensive DFT plan that meets industry standards and company requirements.
- Collaborate with DFT and cross-functional teams to ensure seamless integration of DFT strategies into the overall design process.
- Architect and implement solutions for scan and built-in self-test circuitry to test devices in the field.
- Minimum 5 years of experience in DFT design and implementation is required.
- Strong fundamentals on DFT and ASIC cycle are necessary for success in this role.
- Sound expertise in Tcl, Perl, Shell scripting is a must for effective collaboration with cross-functional teams.
- Hands-on experience with DFT implementation using standard EDA and flow is essential for delivering high-quality results.
- Experience on latest technology (28nm, 16nm, 7nm) is highly desirable.
- B.E./B.S./B.Tech/M.S./M.Tech in VLSI/Electronics/Electrical/Computer/Instrumentation Engineering is preferred.
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