Chief Verification Specialist
2 weeks ago
Senior Design Verification Engineer Job Summary
We are seeking an experienced Senior Design Verification Engineer to lead the functional verification of our PCIe Endpoint IP. The ideal candidate will possess a deep understanding of the PCIe protocol and modern verification methodologies.
Required Skills and Qualifications:- Bachelor's or Master's degree in Electrical/Computer Engineering or related discipline.
- 5+ years of hands-on experience in IP-level RTL verification.
- Deep understanding and verification experience of the PCIe Endpoint protocol (Gen3/Gen4/Gen5 or Gen6).
- Strong command of SystemVerilog, UVM, and industry-standard simulators and debug tools (VCS, Questa, Verdi, etc.).
- Experience writing coverage models, constraints, and assertion-based verification (SVA).
- Strong debugging and analytical skills with the ability to root-cause issues in both RTL and testbench environments.
- Excellent communication and documentation skills.
The Senior Design Verification Engineer will own and drive the functional verification of PCIe Endpoint IP at block and subsystem levels. This includes developing and maintaining SystemVerilog/UVM-based testbenches and reusable verification components (UVCs). The engineer will define and execute detailed verification plans based on functional specifications and architecture documents. They will write and debug testcases, assertions, and checkers to validate PCIe Endpoint behavior, including link training, flow control, power management, and error handling. Additionally, they will drive functional coverage closure and regression stability for IP releases.
BenefitsAs a Senior Design Verification Engineer, you will collaborate closely with RTL design, architecture, and firmware/software teams. You will also support debug and triage of issues discovered during pre-silicon simulation and post-silicon validation. Furthermore, you will continuously improve verification infrastructure, including scripting, automation, and methodology.
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