Senior Verification Engineer

19 hours ago

Thoothukudi, Tamil Nadu, India beBeeVerification Full time ₹ 25,00,000 - ₹ 40,00,000
Senior Verification Engineer - Analog Mixed-Signal IPs and SoCs

This is a key role for a senior verification engineer to lead the development of AMS verification strategies, collaborate with designers to create behavioral models, and drive coverage analysis.

  • Key Responsibilities:
  • Develop and maintain SystemVerilog, Verilog-AMS, or UVM-based verification environments for analog/mixed-signal IPs and SoCs.
  • Perform co-simulation of analog/digital designs using industry tools such as Cadence, Synopsys, and Siemens EDA.
  • Conduct mixed-signal simulations, behavioral modeling of analog blocks, and integration into top-level environments.
  • Collaborate with analog designers to create AMS behavioral models (e.g., Verilog-A/AMS) for early integration and verification.
  • Debug complex AMS simulation issues across multiple abstraction levels.
  • Drive coverage analysis and sign-off using functional, formal, and assertion-based methods.
  • Mentor junior engineers in best practices, methodologies, and tool usage.
  • Evaluate verification deliverables against project timelines and quality standards.

Requirements

A minimum 8+ years of hands-on experience in AMS verification, IP/SoC projects, strong background in mixed-signal simulation, and behavioral modeling required. A Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field necessary.

Benefits

This role offers opportunities for career growth, professional development, and collaboration with experienced engineers.

Preferred Qualifications

Experience with leading cross-functional teams, driving process improvements, and mentoring junior engineers beneficial.

About the Role

The successful candidate will possess excellent technical skills, effective communication and leadership abilities, and a strong understanding of AMS verification principles and practices.

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