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Electrical Engineer
2 weeks ago
We are seeking a talented Design Verification Professional to join our team
Job Description:
The successful candidate will be responsible for the verification of various IPs and/or SoCs.
Key Responsibilities:
- Implement simulation testbenches, low power simulation setup, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target verification goals.
- Develop test-plans, debug failures and analyze coverage information.
- Maintain excellent knowledge of computer architecture and design verification fundamentals.
- Experience with Verilog and popular EDA simulation, System Verilog assertions and testbench methodologies.
- Hands-on experience in developing complex test bench in System Verilog using OVM/UVM methodology.
- Knowledge of AMBA protocol, PCIe MAC, USB MAC, Bluetooth MAC, Wifi 802.11 MAC layer protocol.
- Low Power Simulation/UPF setup, debug low power simulation failures.
- Exposure to scripting languages like Perl, Unix shell or similar languages.
- Good written and oral communication skills necessary.
Requirements:
- 8+ years of design verification experience.
- MS (or higher) in EE/EC/ECC Engineering.
- Candidate must be self-motivated and capable of working independently or as part of a team.
Benefits: