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SoC Design Verification Expert

3 weeks ago

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As a Staff SoC Design Verification Methodology Engineer, you will play a pivotal role in shaping the future of digital technologies.The ideal candidate will possess 6+ years of experience in SoC DV or IP design for high-speed interfaces and be well-versed in System Verilog/UVM/IP Exact/System RDL.Responsibilities will include collaborating with software developers to define feature requirements, creating validation plans, and driving issues to closure.A bachelor's degree in Electronics or an equivalent is required, accompanied by expertise in Git, CI/CD, Linux Scripting, Tcl, and Python.