Technical Leader in Silicon Product Development

2 weeks ago

guntur, India beBeeDigitalTesting Full time

Job Title: Technical Lead in Digital TestingExperience: 7+ YearsLocation: BangaloreIndustry: Semiconductors / ASIC / SoC DesignWe are seeking an experienced DFT Engineer to drive digital testing architecture, planning, and implementation across complex SoC/ASIC designs. As a technical leader, you will mentor junior engineers, collaborate with cross-functional teams, and ensure high-quality testability and manufacturability of silicon products.Main Responsibilities:Digital Test Strategy: Define and implement digital test strategies for multiple ASIC/SoC projects.Implementation and Verification: Lead the implementation and verification of digital test features like scan insertion and compression, ATPG pattern generation and fault grading, MBIST and Logic BIST insertion and validation.Boundary Scan and IJTAG: Implement boundary scan (IEEE 1149.1/1149.6) and IJTAG (1687).Digital Test Flow Management: Manage the end-to-end digital test flow — from RTL to gate-level netlist and silicon bring-up.Cross-Functional Collaboration: Collaborate with RTL, STA, PD, and test engineering teams for seamless integration.Pattern Generation and Debug: Perform pattern generation, fault simulation, and debug test coverage gaps.Digital Test Signoff and Timing Closure: Own DFT signoff, timing closure (DFT-related paths), and ATE pattern delivery.Silicon Bring-Up and Yield Optimization: Support silicon bring-up, test vector validation on ATE, and yield optimization.Mentorship and Training: Mentor and guide junior DFT engineers; conduct design reviews and training sessions.Digital Test Automation: Develop and maintain digital test automation scripts and infrastructure.Required Skills and Experience:Bachelor's or Master's degree in Electronics, Electrical, or VLSI Design.7+ years of experience in digital testing for complex ASIC or SoC designs.Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.Hands-on experience with digital test tools such as Synopsys: DFT Compiler, TetraMAX, TestMAX, Siemens EDA: Tessent ScanPro, MBIST, IJTAG, Cadence/others: Modus, Encounter Test.Strong knowledge of RTL design, STA, and synthesis flows.Proficient in scripting languages (Python, Perl, Tcl) for flow automation.Deep understanding of silicon test challenges and test coverage improvement.Strong leadership, team collaboration, and communication skills.Preferred Qualifications:Experience with hierarchical digital testing and low-power digital testing methodologies.Exposure to post-silicon validation and failure analysis.Familiarity with safety-critical designs and functional safety.Experience working in advanced nodes (e.g., 7nm, 5nm, FinFET).Why Join Us?Lead digital testing for high-performance, next-gen SoCs and ASICs.Collaborate with top-tier engineers and global semiconductor leaders.Competitive salary, leadership exposure, and fast-track growth opportunities.

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